D.Module2.6SLX45T / 6SLX100T
FPGA daughter card for D.Module2 DSP boards
This daughter card, combined with a D.Module2 DSP board, is ideally suited as a main building block for
- ultrasonic and eddy-current material inspection
- measurement and test
- radar and digital radio
- image and video processing
- gigabit speed serial connectivity
The Xilinx Spartan6 LXT FPGA on this daughter board expands a DSP system with data preprocessing and Gigabit speed serial I/O interfaces. In typical applications the FPGA daughter card will provide the interface to high-speed data acquisition devices and implement data preprocessing to relieve the DSP I/O requirements. Postprocessing, analysis, and algorithm control can then be conveniently performed by the DSP system. Additionally the FPGA may implement supplemental peripherals like PWM controller, frame grabber, CAN Bus controller, etc.
Xilinx FPGA Mezzanine Card (FMC) Standard
.
Peripherals and data acquisition subsystems are connected to the FPGA board through max. 98 user definable single-ended signals (48 LVDS signal pairs), and up to three Gigabit links. These I/Os conform to the industry standard VITA 57 FMC specification. A suitable prototyping platform, the D.Module2.Base-FMC, with D.Module2 and a FMC LPC mezzanine site is available.
The DSP is by default connected to the FPGA via the D.Module2 32-bit wide parallel bus interface. Depending on the DSP capabilities alternative data paths exist: Serial Rapid IO (SRIO) on the GTP connector and LVDS (e.g. TigerSHARC® Link Ports) on the EXP connector. The EXP signals are available as free user-programmable I/O if not used for DSP-FPGA communication, e.g. as a base mode CameraLink.
The Spartan6 GTPs (Gigabit Transceivers) provide additional high-speed connectivity interfaces like SRIO for inter-board communications, JESD204/A as a high-speed A/D and D/A interface, SGMII to interface a Gigabit Ethernet PHY, SATA, DisplayPort 1.1, and PCIe v1.1.
The DSP has full access to the FPGA configuration Flash Memory and can re-configure and update the FPGA at any time. Other key features are programmable I/O voltage, 128M Bytes local DDR3 RAM and a JTAG interface for FPGA programming and debugging via Xilinx ChipScopeTM.
A block diagram, typical applications, and more information about the D.Module2.6SLX45T, is provided in the interactive tour.
| Product Features | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FPGA | Xilinx Spartan6 | default: XC6SLX45T, optional XC6SLX100T
|
||||||||||||||||||||||||
| Memory | DDR3 | 128M Bytes, 333MHz | ||||||||||||||||||||||||
| Configuration | 8M Bytes SPI Flash Memory | |||||||||||||||||||||||||
| Clock Resources | external | BUSCLK (from DSP module) 4 single-ended (2 LVDS) global clock nets on EXP connector 12 single-ended (6 LVDS) clock nets on BUS1 and BUS2 connectors 2 LVDS reference clocks for Gigabit Transceivers |
||||||||||||||||||||||||
| internal programmable clock synthesizer | AUXCLK two reference clocks for Gigabit Transceivers |
|||||||||||||||||||||||||
| DSP Interface | Parallel Bus | 32 data bits, 20 address lines, 10 control lines,
synchronous pipelined and/or asynchronous operation (depending on DSP
capabilities) |
||||||||||||||||||||||||
| LVDS | 8 data lines, 2 clocks, 2 control lines (e.g. Link Ports on D.Module2.TS203) usable as addtional User-I/O if not used for DSP-FPGA communications. |
|||||||||||||||||||||||||
| SRIO | one lane, up to 3.125Gb/s | |||||||||||||||||||||||||
| Misc. | 4 GPIO 3 Interrupts 2 Serial Ports |
|||||||||||||||||||||||||
| Gigabit Transceivers | 4 | one routed to top connector (DSP SRIO interface), 3 on bottom side connector for User-I/O, supporting PCIe (1x, v1.1), SGMII, JESD204/A, SATA, SRIO, DisplayPort 1.1 |
||||||||||||||||||||||||
| User I/O | default | 74 single-ended / 36 LVDS, VITA 57 FMC compatible | ||||||||||||||||||||||||
| maximum | 98 single-ended / 48 LVDS if EXP signals not used for DSP interface | |||||||||||||||||||||||||
| I/O Voltage | programmable | 1.8, 2.5, 3.3V | ||||||||||||||||||||||||
| Power Supply | 3.3V | single supply | ||||||||||||||||||||||||
| Mechanics | 87 x 58 x 15 mm | self-stacking design, board-spacing 10mm IEEE-1386 high-density connectors |
||||||||||||||||||||||||
| RoHS conformity | yes | |||||||||||||||||||||||||
back to top| Data Sheets and Application Notes | |
|---|---|
| tdd2fpga6lxt.pdf | 
technical data sheet |
| User's Guide, Support Software, Updates | available for registered customers |
| tdd2basefmc.pdf |
D.Module2 FMC base board technical data sheet |
| Development Tools | |
|---|---|
| DS.6SLX45T | D.Module2.5SLX45T Development Base Package including User's Guide, VHDL source files and projects, DSP sample programs |
| D2.Base-FMC | Evaluation and Prototyping Base Board with FMC and D.Module2 site, Power Supply, PCIe, Ethernet, and USB connectors |
| Order Information | |
|---|---|
| D.Module2.6SLX45T | standard module with XC6SLX45T FPGA |
| D.Module2.6SLX100T | with XC6SLX100T FPGA |
| DS.6SLX45T | Development Base Package |
| D2.Base-FMC | Prototyping Platform with FMC site |
| Please contact us or our international resellers for price, delivery, and volume discount information | |
| © D.SignT 1998-2011 | comments: webmaster@dsignt.de | Impressum / Imprint | last change: 2011-11-22 |