D.Module2.6SLX45T - Interactive Tour

COM Connector

• USB 2.0
• 100Base-Tx Ethernet
• RS232 and RS422
• I²C
• GPIO (16 signals)

These signals are interconnected from top to bottom connector to allow direct access to the DSP board communication interfaces. Except I²C none of these signals is connected to the FPGA. I²C is used for board control (I/O power supply, FPGA Configuration, etc.).

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BUS1 and BUS2 Connector, bottom side

• FMC_CLK[1:0]_M2C_P/N (GCLK)
• FMC_LA[01:00]CC_P/N (GCLK)
• FMC_LA[16:02]_P/N
• FMC_LA[18:17]CC_P/N (GCLK)
• FMC_LA[33:19]_P/N
• FMC_PG_C2M
• FMC_PRSNT
• DSP sync. serial port 1
• DSP GPIO[3:2]

These signals form the main interface for external hardware to FPGA banks 0 and 2. All signals are routed as differential pairs with matched lengths to minimize skew in high-speed applications. Signal names have been chosen to comply with the FMC Mezzanine standard, but of course any arbitrary hardware can be attached.
The programmable I/O voltage supports LVTTL, LVCMOS (3.3, 2.5, and 1.8V) and LVDS I/O standards. Also supported are SSTL and HSTL which require a reference voltage, but at the expense of less avaialble I/O pins.
 
Connected to both BUS2 connectors and the FPGA are one of the DSP synchronous serial ports (TI: McASP/McBSP, ADI: SPORT) and two DSP GPIO signals. Depending on the configuration these signals can be used as as additional FPGA-I/O or as a direct connection to the DSP (e.g. for supplementary A/D converters which do not require FPGA preprocessing).

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BUS1 and BUS2 Connector, top side

• Bus DATA[31:0]
• Bus ADDR[19:0]
• Bus CTRL signals
• Interrupts
• DSP sync. serial port 0
• DSP sync. serial port 1
• DSP GPIO[3:0]

This is the DSP external bus interface. Depending on the DSP, synchronous pipelined and asynchronous access is supported. These signals are available on all D.Module2.DSP boards as DSP - FPGA interface.
Also available on the BUS2 connector and connected to the FPGA are two DSP synchronous serial ports (TI: McASP/McBSP, ADI: SPORT) and four DSP GPIO signals.

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EXP Connector

One half of the bottom Expansion connector is directly connected to the top-side EXP connector, providing direct access to the DSP Expansion signals. No FPGA I/Os are connected here.
The second half is routed to the FPGA and, via a bus switch, also to the top EXP connector. This allows to use these signals as either FPGA I/O resources, as a direct connection to the DSP expansion signals, or as an alternative DSP - FPGA interface. The latter is supported by the D.Module2.TS203: the TigerSHARC link ports.
 
Connected to the FPGA Bank 2 are 24 single-ended or 12 LVDS signals:

• EXP_DAT[7:0]_P/N
• EXP_CLK[1:0]_P/N (GCLK)
• EXP_CTL[1:0]_P/N

If not used for the DSP interface, these signals may for example be configured as a base mode CameraLink Interface.

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GTP Top Connector

One Gigabit Transceiver for DSP - FPGA communications is routed to the FPGA, typically used as Serial Rapid IO (SRIO). Another GTP pair plus a reference clock is routed to the bottom side GTP connector for direct access to a DSP Gigabit Transceiver, typically PCIe.

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GTP Bottom Connector

Three Gigabit Transceivers, two GPIO signals, and two reference clock inputs are available on this connector, plus a direct connection to a DSP PCIe transceiver. GTPs can be used as Serial Rapid IO (SRIO) for inter-system communications, JESD204 interface to high speed A/D and D/A converters, a PCIe link to a PC, SATA, or as SGMII to attach Gigabit Ethernet PHYs.

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Board Control

• Configuration Flash programming
• initiate and supervise FPGA configuration
• configure the clock synthesizer
• configure Bank 0 and 2 VCCIO supply
• board temperature monitoring

Via I²C the DSP has full control over the FPGA board. Access to the FPGA Configuration Flash Memory and the configuration I/O signals enables in-system and remote updates.

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DDR3 Memory

128M bytes DDR3 memory operating at 333MHz (DDR3-1066) provide ample storage for large data acquisition buffers and delay lines. The Spartan6 dedicated memory controller handles intialization and access with minimum logic usage.

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Spartan6 FPGA

The Spartan6 LXT family is optimized for

• high speed serial connectivity
• support of a wide variety of I/O standards
• efficient DSP slices with 18x18 multiplier and 48-bit accumulator
• integrated memory controller block
• integrated PCI Express (PCIe) endpoint block
• externsive clock management

Bank 0 and 2 are used for external I/O. All global clock inputs are accessible, the VCCIO voltage is programmable via I2C.
Bank 1 forms the parallel bus DSP interface, Bank 3 interfaces to 128M bytes DDR3 memory.
An I2C programmable clock synthesizer generates an auxiliary global FPGA clock and two reference clocks for the MGT Gigabit transceiver blocks.
An SPI Flash Memory stores the FPGA configuration. At power-on the FPGA is automatically configured. The DSP has full access to this configuration memory and to the FPGA configuration I/O signals for in-system and remote updates and re-configuration.
A JTAG interface is provided for configuration during development and as a debugging interface using Xilinx ChipScope.

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