Comparison Chart D.Module2.C6657 - Texas Instruments C66x Keystone DSPs
This chart compares the resources and interfaces available on the D.Module2.C6657 with other Texas Instruments Keystone DSP family members (single-core and multi-core C665x and C667x devices). Features not shown in this table are identical throughout the C66x Keystone family.
| D.Module2.C6657 | TMS320C6654 | TMS320C6655 | TMS320C6670 | TMS320C6671 | TMS320C6672 | TMS320C6674 | TMS320C6678 | |
| cores | 2 | 1 | 1 | 4 | 1 | 2 | 4 | 8 |
| max. core clock | 1250 MHz | 850 MHz | 1250 MHz | 1200 MHz | 1250 MHz | 1500 MHz | 1250 MHz | 1250 MHz |
| peak MMACs | 80000 | 27200 | 40000 | 153000 | 40000 | 96000 | 160000 | 320000 |
| hardware accelerators | VCP2, TCP3d | - | VCP2, TCP3d | VCP2, TCP3d, TCP3e, FFT, PA | PA | PA | PA | PA |
| internal L2 RAM | 3072K | 1024K | 2048K | 6144 K | 4608K | 5120K | 6144K | 8192K |
| DDR3 Interface | 32-bit DDR3-1333 | 32-bit DDR3-1066 | 32-bit DDR3-1333 | 64-bit DDR3-1600 | 64-bit DDR3-1600 | 64-bit DDR3-1600 | 64-bit DDR3-1600 | 64-bit DDR3-1600 |
| PCIe | 2 lanes | 2 lanes | 2 lanes | 2 lanes | 2 x 2 lanes | 2 x 2 lanes | 2 x 2 lanes | 2 x 2 lanes |
| SRIO | 2 lanes | - | 4 lanes | 4 lanes | 4 lanes | 4 lanes | 4 lanes | 4 lanes |
| Gigabit Ethernet | 1 | 1 | 1 | 2 + Switch | 2 + Switch | 2 + Switch | 2 + Switch | 2 + Switch |
| McBSP | 2 | 2 | 2 | - | - | - | - | - |
| TSIP | - | - | - | 2 | 2 | 2 | 2 | |
| AIF2 | - | - | - | 6 | - | - | - | - |
| EMIF | 16-bit | 16-bit | 16-bit | - | 16-bit | 16-bit | 16-bit | 16-bit |
| UPP | 2 ports | 2 ports | 2 ports | - | - | - | - | - |