D.Module2.6SLX45T
The D.Module2.6SLX45T is based on the Xilinx Spartan-6 FPGA XC6SLX45T. In the D.Module2 family it can be used to implement additional interfaces or as a data preprocessing engine if hooked between a data acquisition card and a DSP module.
Up to 96 single-ended or 48 differential I/O signals are available. Programmable I/O voltages and I/O standards provide glueless system integration. Three gigabit transceivers are available to interface high-speed data converters in JESD204 standard, or as PCI/e or SATA interfaces. All D.Module2 DSP boards support a parallel bus interface to the D.Module2.6SLX45T. Depending on the DSP capabilities, alternative interfaces can be used: Link Ports, Serial Rapid IO, VLYNQ, or Fifo-based interface such as UPP or Video Ports.
The D2.Base-FMC base board provides an interface and a test and evaluation platform for FPGA Mezzanine Cards conforming to the Vita.57 LPC FMC standard.
Key Features
- Spartan XC6SLX45T FPGA extension board
- high-speed parallel DSP interface
- PCIe, JESD204
- 98 User-I/Os
- 128 Mbytes local RAM
- configuration update via DSP-board
- 3.3V single supply
Applications
The D.Module2.6SLX45T provides an extremely versatile solution to implement interfaces and to preprocess high-speed data converters.
- PWM output for motor control
- Camera Link interface for industrial image processing
- Data acquistion and preprocessing of high-speed A/D and D/A converters on FMC mezzanine cards or JESD-204 standard for ultrasonic, radar, and Software Defined Radio (SDR) applications
- SATA controller for data logging
- Field bus implementation
| FPGA | Xilinx Spartan-6 | XC6SLX45T |
| Memory | DDR3 | 128M bytes, DDR3-1066 |
| Configration | SPI Flash Memory | 8M bytes |
| Clocks | onboard | Si5338 clock synthesizer, I²C programmable, generates AUXCLK and GTP reference clocks. |
| external | 16 single-ended / 8 LVDS global clock inputs | |
| DSP Board Interface | parallel | 32 data bits, 20 address lines, 10 control lines, synchronous pipelined and/or asynchronous operation (depending on DSP capabilities) |
| serial | 1 x Link Port (with D.Module2.TS203) | |
| 1 x SRIO, one lane, up to 3.125Gb/s | ||
| 2 x McBSP / SPORT port | ||
| Misc. | 4 interrupt lines, 3 GPIO | |
| External Ports | default | 74 single-ended / 36 LVDS |
| max. | 96 single-ended / 48 LVDS | |
| IO voltage | programmable onboard supply: 1.8, 2.5, or 3.3V | |
| Gigabit Transceivers | 3, supporting PCI/e 1.1, JESD204/A, SATA, SRIO | |
| Programming Interface | JTAG via Xilinx Programming Cable, I2C via DSP board | |
| Power Supply | 3.3V single supply | |
| Temperature Range | 0 – 70°C | |
| Connectors | BUS1, BUS2, COM, EXP | bottom side: Molex 71436-2164, top side: 71439-0164 |
| PCIe / SRIO | bottom side: Molex 46556-1145, top side: 46557-1545 | |
| JTAG | 14-pin, 2.0 mm pitch | |
| Mechanics | 86.8 x 58.4 mm, overall height: 18mm, stacked height: 11mm | |
| ROHS | compliant |
The D.Module2.6SLX45T may be equipped with a different Spartan-6 FPGA on request.
| D.Module2.6SLX45T | standard module |
| D.Module2.6SLX100T | OEM option, Spartan-6 XC6SLX100T FPGA |
| DS.6SLX45T | software development package including sample programs (FPGA and DSP) |
The D.Module2.6SLX45T may be used as an alternative to other members of the Xilinx Spartan-6 family. The following resource compares the D.Module2.6SLX45T features with other Spartan-6 FPGAs.