CCS GEL file

Use GEL file dm2dm642.gel in conjunction with CodeComposer Studio to get the D.Module2.DM642 into a reset and initialized state.

/********************************************************************//**
 @file dm2dm642.gel
 @brief @ref P_CCSGEL "D.Module2.DM642 GEL File"

 @author    D.SignT GmbH & Co. KG, A.Klemenz
 @date      2012-09-26

 @version 1.1
 @target D.Module2.DM642

 @details This GEL file is to be used with the D.Module2.DM642.

 Code Composer Studio supports six reserved GEL functions that
 automatically get executed if they are defined. They are:

 - StartUp()              - Executed whenever CCS is invoked
 - OnReset()              - Executed after Debug->Reset CPU
 - OnRestart()            - Executed after Debug->Restart
 - OnPreFileLoaded()      - Executed before File->Load Program
 - OnFileLoaded()         - Executed after File->Load Program
 - OnTargetConnect()      - Executed after Debug->Connect

***********************************************************************/


#define EMIFCLK 133000000
#define UARTCLK 48000000


/***********************************************************************
  StartUp() is called each time CCS is started
  OnTargetConnect is called after Debug->Connect
***********************************************************************/
StartUp()
{
}


/***********************************************************************
  on device reset:
***********************************************************************/
OnReset()
{
    D2DM642_InitEmif(EMIFCLK); // Parameter: EMIF Clock 83,100,125,133
    *(int *)0x3FC = UARTCLK;
}


/***********************************************************************
  called on debug->restart
***********************************************************************/
OnRestart()
{
/* CCS will call OnRestart() when you do a Debug->Restart and   */
/* after you load a new file.  Between running interrupt based  */
/* programs, this function will clear interrupts and help keep  */
/* the processor from going off into invalid memory.            */

      /* Turn off cache for SDRAM */
      *(int *)0x1848200 = 0;  /* MAR0 */
      *(int *)0x1848204 = 0;  /* MAR1 */
      *(int *)0x1848208 = 0;  /* MAR2 */
      *(int *)0x184820C = 0;  /* MAR3 */

      /* Disable EDMA events */
      *(int *)0x01A0FFA8 = 0;          /* CIERH */
      *(int *)0x01A0FFB4 = 0;          /* EERH */
      *(int *)0x01A0FFB8 = 0XFFFFFFFF; /* ECRH */

      *(int *)0x01A0FFE8 = 0;          /* CIERL */
      *(int *)0x01A0FFF4 = 0;          /* EERL */
      *(int *)0x01A0FFF8 = 0xFFFFFFFF; /* ECRL */

      /* Disable interrupts */
      IER = 0;
      IFR = 0;
}


/***********************************************************************
  called on load program
***********************************************************************/
OnPreFileLoaded()
{
    GEL_Reset();
    FlushCache();
    IER = 0;
    IFR = 0;
    D2DM642_InitEmif(EMIFCLK); // Parameter: EMIF Clock 83,100,125,133
}

OnFileLoaded(int nErrorCode, int bSymbolsOnly)
{
  if (!bSymbolsOnly)
  {
//     ADC_Cal();
  }
}

OnTargetConnect()
{
    MemoryMap();
    D2DM642_InitEmif(EMIFCLK); // Parameter: EMIF Clock 83,100,125,133
    GEL_Reset();
}


/***********************************************************************
  initialize EMIF
***********************************************************************/
D2DM642_InitEmif(eclk)
{
    #define EMIF_GCTL   0x01800000
    #define EMIF_CECTL1 0x01800004
    #define EMIF_CECTL0 0x01800008
    #define EMIF_CECTL2 0x01800010
    #define EMIF_CECTL3 0x01800014
    #define EMIF_SDCTL  0x01800018
    #define EMIF_SDTIM  0x0180001C
    #define EMIF_SDEXT  0x01800020
    #define EMIF_PDTCTL 0x01800040
    #define EMIF_CESEC1 0x01800044
    #define EMIF_CESEC0 0x01800048
    #define EMIF_CESEC2 0x01800050
    #define EMIF_CESEC3 0x01800054
    #define EMIF_CCFG   0x01840000

    *(int *)EMIF_GCTL   = 0x00010020;
    *(int *)EMIF_CECTL0 = 0x000040D0;   // 64-bit SDRAM
    *(int *)EMIF_CECTL1 = 0x21614511;   // 16-bit asynchronous
    *(int *)EMIF_CECTL2 = 0x11114421;   // 32-bit asynchronous
    *(int *)EMIF_CECTL3 = 0x11114421;   // 32-bit asynchronous
    *(int *)EMIF_CESEC0 = 0x00000000;
    *(int *)EMIF_CESEC1 = 0x00000040;
    *(int *)EMIF_CESEC2 = 0x0000007F;
    *(int *)EMIF_CESEC3 = 0x0000007F;

    if (eclk == 83000000)
    {
        *(int *)EMIF_SDTIM = 0x00516516;
        *(int *)EMIF_SDEXT = 0x0004B4A6;
        *(int *)EMIF_SDCTL = 0x53114000;
    }
    else if (eclk == 100000000)
    {
        *(int *)EMIF_SDTIM = 0x0061A61A;
        *(int *)EMIF_SDEXT = 0x0004B4A6;
        *(int *)EMIF_SDCTL = 0x53115000;
    }
    else if (eclk == 125000000)
    {
        *(int *)EMIF_SDTIM = 0x007A17A1;
        *(int *)EMIF_SDEXT = 0x0005452B;
        *(int *)EMIF_SDCTL = 0x53227000;
    }
    else if (eclk == 133000000)
    {
        *(int *)EMIF_SDTIM = 0x00823823;
        *(int *)EMIF_SDEXT = 0x0005452B;
        *(int *)EMIF_SDCTL = 0x53227000;
    }
    else
    {
        GEL_TextOut(" ERROR! unsupported EMIF Clock ");
    }
}


/***********************************************************************
  Flush L1 and L2 cache
***********************************************************************/
FlushCache()
{
    /* Invalidate L1I and L1D */
    *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);

    /* Clean L2 */
    *(int *)0x01845004 = 0x1;
}





/***********************************************************************
  define the memory_map
***********************************************************************/
MemoryMap()
{
    GEL_MapOn();
    GEL_MapReset();
    GEL_MapAdd(0x00000000,0,0x80000000,1,1); // internal RAM and on-chip peripherals
    GEL_MapAddStr(0x80000000, 0, 0x10000000, "R|W|AS8", 0); // 64 bit RAM
    GEL_MapAddStr(0x90000000, 0, 0x10000000, "R|W|AS2", 0); // 16 bit RAM
    GEL_MapAddStr(0xA0000000, 0, 0x10000000, "R|W|AS4", 0); // 32 bit RAM
    GEL_MapAddStr(0xB0000000, 0, 0x10000000, "R|W|AS4", 0); // 32 bit RAM
}



/***********************************************************************
  GEL Menue
***********************************************************************/
menuitem "Resets";

hotmenu ClearBreakPts_Reset()
{
   GEL_BreakPtReset();
   GEL_Reset();
}

hotmenu Flush_Cache()
{
   FlushCache();
}


menuitem "D.Module2.DM642";

hotmenu InitializeEMIF()
{
    D2DM642_InitEmif(EMIFCLK); // Parameter: EMIF Clock 83,100,125,133
}