Search results

Create the page "Clock" on this wiki! See also the search results found.

Page title matches

• D2c6747 higher cpu clock
  ...TMS320C6747BZKB3 used on the D.Module2.C6747 Rev. 1.1 supports 375 MHz CPU clock. * CPU clock (SYSCLK1) = 360 MHz (org: 300 MHz)
  2 KB (316 words) - 15:34, 15 December 2011

Page text matches

• D2ts203 timer
  ...TMR0E output (pulse), or the output of a toggle-flipflop driven by TMR0E (clock). The toggle-flipflop will divide the timer output by 2 and provide 50% dut The timer input clock is SYSCLK. To initialize and start the timer use:
  2 KB (307 words) - 01:29, 18 February 2011
• D2c6747 higher cpu clock
  ...TMS320C6747BZKB3 used on the D.Module2.C6747 Rev. 1.1 supports 375 MHz CPU clock. * CPU clock (SYSCLK1) = 360 MHz (org: 300 MHz)
  2 KB (316 words) - 15:34, 15 December 2011
• Cascading two ADDA16 boards
  ...ut. The second board is configured to external sampling clock. To feed the clock output from board1 to the input of board2 connects pins C22 to pin C23: 5. to use an external sampling clock for both boards, feed this clock to EXTCLK_IN (C22) of both boards. The solftware configuration is:
  5 KB (597 words) - 11:10, 4 July 2011
• Writing interruptible code on C6xxx DSPs
  value specifies the maximum number of clock cycles that the compiler can disable
  2 KB (325 words) - 16:09, 15 December 2011