D2c6747 higher cpu clock

1 Problem

The TMS320C6747BZKB3 used on the D.Module2.C6747 Rev. 1.1 supports 375 MHz CPU clock. The default configuration of the board is 300MHz. Is it possible to use 375MHz?

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2 Solution

If the Ethernet Port is not used, it is possible to configure the board to 360 MHz operation with

CPU clock (SYSCLK1) = 360 MHz (org: 300 MHz)
EMIFA Clock (SYSCLK3) = 90 MHz (org: 100 MHz)
EMIFB clock (SYSCLK5, SDRAM) = 120MHz (org: 133 MHz)

The RMII_CLK for the Ethernet Interface is generated from SYSCLK7 in the DSP. There is no suitable divider setting to obtain the required 50MHz with the above configuration. This is only possible if the CPU clock is a multiple of 50MHz: 300 or 350MHz, but 350MHz cannot be generated from the 24MHz input clock (which in turn is required for the USB interface).

Board Revision 1.2 will add an extra oscillator for RMII_CLK. This will allow 1.2 boards to operate at up to 456 MHz with TMS320BZKB4 processors with full functionality. Supported configurations are:

CPU 300 MHz, EMIFA 100 MHz, SDRAM 133MHz
CPU 360 MHz, EMIFA 90 MHz, SDRAM 120MHz
CPU 396 MHz, EMIFA 99 MHz, SDRAM 132MHz
CPU 456 MHz, EMIFA 91 MHz, SDRAM 114MHz

To change the clock options add the following code at the start of your main program:

#define CPUCLK 360                /* 396 or 456 possible for TMS320C6747BZKB4 */

#if CPUCLK==360
  DM2_hwSettings.pll_pllm = 29;    /* 360 MHz CPU clock */
  DM2_hwSettings.pll_plldiv3 = 3;  /*  90 MHz EMIFA clock */
  DM2_hwSettings.pll_plldiv5 = 2;  /* 120 MHz EMIFB clock */
  DM2_hwSettings.pll_cfgchip3 = 0; 
#endif

#if CPUCLK==396
  DM2_hwSettings.pll_pllm = 32;    /* 396 MHz CPU clock */
  DM2_hwSettings.pll_plldiv3 = 3;  /*  99 MHz EMIFA clock */
  DM2_hwSettings.pll_plldiv5 = 2;  /* 132 MHz EMIFB clock */
  DM2_hwSettings.pll_cfgchip3 = 0; 
#endif

#if CPUCLK==456
  DM2_hwSettings.pll_pllm = 37;    /* 456 MHz CPU clock */
  DM2_hwSettings.pll_plldiv3 = 4;  /*  91 MHz EMIFA clock */
  DM2_hwSettings.pll_plldiv5 = 3;  /* 114 MHz EMIFB clock */
  DM2_hwSettings.pll_cfgchip3 = 0; 
#endif

  DM2_init(DM2_INIT_PLL);