Cascading two ADDA16 boards

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1 Problem

Cascading two ADDA16 boards for an 8-channel data acquisition system

2 Solution

1. Both boards need to be configured to different I/O addresses. Leave the first board in the default factory setting and close jumper JPA4 on the second board.

2. The default header file adda16.h does not provide macros for a dual configuration. Create a new header file adda16_dual.h for use in your project:

#define ADDA16_1_OFFSET   0x000000   
#define ADDA16_2_OFFSET   0x000040   

#define ADDA16_1_BASE     (IOSEL_BASE + ADDA16_1_OFFSET)
#define ADDA16_2_BASE     (IOSEL_BASE + ADDA16_2_OFFSET)

typedef struct
    volatile short rsvd0;
    volatile short ch0;
    volatile short rsvd1;
    volatile short ch1;
    volatile short rsvd2;
    volatile short ch2;
    volatile short rsvd3;
    volatile short ch3;
    volatile short rsvd4;
    volatile unsigned short fs;
    volatile short rsvd5;
    volatile unsigned short cfg;
} adda16_type;

#define ADDA16_1 ((adda16_type *) ((unsigned int *)ADDA16_1_BASE))
#define ADDA16_2 ((adda16_type *) ((unsigned int *)ADDA16_2_BASE))

  Macros to read ADC and write DAC:
#define ADDA16_1_READ_ADC(ch)       (*(volatile short*)(ADDA16_1_BASE+2+(ch<<2)))
#define ADDA16_1_WRITE_DAC(ch,val)  (*(volatile short*)(ADDA16_1_BASE+2+(ch<<2)) = val)
#define ADDA16_2_READ_ADC(ch)       (*(volatile short*)(ADDA16_2_BASE+2+(ch<<2)))
#define ADDA16_2_WRITE_DAC(ch,val)  (*(volatile short*)(ADDA16_2_BASE+2+(ch<<2)) = val)

the remainder of the header file is identical to adda16.h:


  ADDA16 Sampling Frequency Register

/* common sampling frequencies */
#define ADDA16_FS250    0x000F
#define ADDA16_FS200    0x0013
#define ADDA16_FS160    0x0018
#define ADDA16_FS120    0x001F
#define ADDA16_FS100    0x0027
#define ADDA16_FS80     0x0031
#define ADDA16_FS67     0x003B
#define ADDA16_FS50     0x004F
#define ADDA16_FS33     0x0077
#define ADDA16_FS25     0x009F
#define ADDA16_FS20     0x00C7
#define ADDA16_FS16     0x00F9
#define ADDA16_FSEXT    0x0000

/* this macro can be used for any integer sampling frequency from 15625 Hz to 250 kHz */
#define ADDA16_FS(x)    ((4000000/(int)x)-1)


  ADDA16 Configuration Register

#define ADDA16_DAC_READY 0x0080  /* read : DAC ready for new transfer */
#define ADDA16_EXTCLK_ON 0x0080  /* write: turn on EXTCLK output */

#define ADDA16_INT1DAC   0x0040  /* map DAC to nINT1 */
#define ADDA16_INT1ADC   0x0020  /* map ADC to nINT1 */
#define ADDA16_INT1FS    0x0060  /* map sampling frequency to nINT1 */
#define ADDA16_INT0DAC   0x0010  /* map DAC to nINT0 */
#define ADDA16_INT0ADC   0x0008  /* map ADC to nINT0 */
#define ADDA16_INT0FS    0x0018  /* map sampling frequency to nINT0 */

#define ADDA16_LDAC_ANY  0x0000  /* update DACs after any DAC write */
#define ADDA16_LDAC_2    0x0001  /* update DACs after writing to DAC 2 */
#define ADDA16_LDAC_3    0x0002  /* update DACs after writing to DAC 3 */
#define ADDA16_LDAC_4    0x0003  /* update DACs after writing to DAC 4 */
#define ADDA16_LDAC_FS   0x0004  /* use ADC sampling frequency to update DACs */

3. The ADDA16 is shipped with some spare D.Module connectors. Press two of these connector pins into locations C22 and C23 on both ADDA16 boards.

4. To use internal sampling clock configure the first board to generate the sampling clock and enable its EXTCLK_OUT output. The second board is configured to external sampling clock. To feed the clock output from board1 to the input of board2 connects pins C22 to pin C23:

   ADDA16_1->fs  = ADDA16_FS(125000);
   ADDA16_1->cfg = (ADDA16_INT0ADC | ADDA16_EXTCLK_ON | ADDA16_LDAC_FS);
   ADDA16_2->fs  = ADDA16_FSEXT;
   ADDA16_2->cfg = ADDA16_LDAC_FS;

5. to use an external sampling clock for both boards, feed this clock to EXTCLK_IN (C22) of both boards. The solftware configuration is:

   ADDA16_1->fs  = ADDA16_FSEXT;
   ADDA16_1->cfg = (ADDA16_INT0ADC | ADDA16_LDAC_FS);
   ADDA16_2->fs  = ADDA16_FSEXT;
   ADDA16_2->cfg = ADDA16_LDAC_FS;

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