D2ts203 bus interface
1 Problem
DMA reads from external bus interface in synchronous mode do not work as expected
SYNC and READ_REG configuration bits are accidently inverted in the board logic. If the bus is configured to synchronous mode it actually works in asynchronous mode and vice versa.
The issue has no effect on asynchronous transfers, except all signals are delayed by one cycle, which is not visible if only the external bus signals are observed. Everything looks "normal".
It also has no effect on synchronous writes: again all signals appear "normal". There is no obvious effect on synchronous single-word reads, as long as only one external device is attached to the external bus interface: the bus-hold feature of the bus drivers keeps the data from the previous read cycle stable. Successive data is therefore correctly read, but with a one read cycle latency.
Finally this issue has also no effect on FlyBy transfers because the bus is controlled by the DSP IORD and IOWR signals, ADDR, RD_N, WR_N, and CSxN, which timings are affected by the SYNC configuration bit, are not used in FlyBy mode.
Only DMA burst transfers are affected.
2 Solution
The board logic (CPLD) and bus logic (GAL) have been corrected. All boards starting with serial no # 10016 include this fix.
3 Additional Tags
synchronous bus interface DMA
Contact 
Support 
